Pixel circuit and driving method thereof, and display device

ABSTRACT

A pixel circuit and a driving method thereof, and a display device are provided. The pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a first light-emitting control sub-circuit, a second light-emitting control sub-circuit, a compensation sub-circuit, and a first reset sub-circuit, and is configured to generate a driving current to control a light-emitting element to emit light, the first reset sub-circuit comprises a first transistor, the compensation sub-circuit comprises a second transistor, the first transistor and the second transistor are both polysilicon oxide thin film transistors, and an active layer type of the first transistor and an active layer type of the second transistor are different from an active layer type of a transistor comprised in at least one selected from a group consisting of the driving sub-circuit, the data writing sub-circuit, the first light-emitting control sub-circuit, and the second light-emitting control sub-circuit.

This application is a continuation of U.S. patent application Ser. No.17/639,599 filed on Mar. 2, 2022, which is a national phase ofInternational Patent Application No. PCT/CN2021/091234, filed on Apr.30, 2021. All the aforementioned patent applications are herebyincorporated by reference in their entireties.

TECHNICAL FIELD

At least one embodiments of the present disclosure relates to a pixelcircuit and a driving method thereof, and a display device.

BACKGROUND

An organic light emitting diode (OLED) is an active light emittingdisplay device, has the advantages of self-illumination, wide viewingangle, high contrast, low power consumption, extremely high responsespeed, and so on, and has been widely used in display products such as amobile phone, a tablet computer, and a digital camera. The OLED displaybelongs to a current drive, a current needs to be output to the OLEDthrough a pixel circuit to drive the OLED to emit light.

SUMMARY

At least one embodiment of the present disclosure provides a pixelcircuit, comprising a driving sub-circuit, a data writing sub-circuit, afirst light-emitting control sub-circuit, a second light-emittingcontrol sub-circuit, a compensation sub-circuit, and a first resetsub-circuit, and the pixel circuit is configured to generate a drivingcurrent to control a light-emitting element to emit light, the drivingsub-circuit comprises a control terminal, a first terminal, and a secondterminal; the data writing sub-circuit is electrically connected to thefirst terminal of the driving sub-circuit and a data signal terminal,and is configured to write a data signal of the data signal terminalinto the first terminal of the driving sub-circuit in response to asignal of a first scan signal terminal; the compensation sub-circuit iselectrically connected to the second terminal of the driving sub-circuitand the control terminal of the driving sub-circuit, and is configuredto perform threshold compensation on the driving sub-circuit in responseto a signal of a compensation control signal terminal; the firstlight-emitting control sub-circuit is electrically connected to thefirst terminal of the driving sub-circuit and a first voltage terminal,and is configured to achieve a connection between the drivingsub-circuit and the first voltage terminal to be turned on or off inresponse to a signal of a light-emitting signal control terminal; thesecond light-emitting control sub-circuit is electrically connected tothe second terminal of the driving sub-circuit and a first electrode ofthe light-emitting element, and is configured to achieve a connectionbetween the driving sub-circuit and the light-emitting element to beturned on or off in response to the signal of the light-emitting signalcontrol terminal; and the first reset sub-circuit is electricallyconnected to the second terminal of the driving sub-circuit and a secondvoltage terminal, and is configured to write a signal of the secondvoltage terminal into the second terminal of the driving sub-circuit inresponse to a signal of a second scan signal terminal; the first resetsub-circuit comprises a first transistor, the compensation sub-circuitcomprises a second transistor, the first transistor and the secondtransistor are both polysilicon oxide thin film transistors, and anactive layer type of the first transistor and an active layer type ofthe second transistor are different from an active layer type of atransistor comprised in at least one selected from a group consisting ofthe driving sub-circuit, the data writing sub-circuit, the firstlight-emitting control sub-circuit, and the second light-emittingcontrol sub-circuit.

For example, the pixel circuit provided by at least one embodiment ofthe present disclosure further includes a second reset sub-circuit, thesecond reset sub-circuit is electrically connected to the firstelectrode of the light-emitting element and a third voltage terminal,and is configured to write a signal of the third voltage terminal intothe first electrode of the light-emitting element in response to asignal of a reset control signal terminal to reset the first electrodeof the light-emitting element.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, the first scan signal terminal and the resetcontrol signal terminal are connected to an identical signal line.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, the data writing sub-circuit comprises a thirdtransistor, in a case where the pixel circuit is in a first displaymode, a turn-on frequency of the third transistor is greater than aturn-on frequency of the second transistor, and in a case where thethird transistor and the second transistor are both turned on, the datasignal is transmitted to the control terminal of the drivingsub-circuit.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, a voltage value of the signal of the thirdvoltage terminal is greater than a voltage value of the signal of thesecond voltage terminal.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, the second reset sub-circuit comprises a seventhtransistor, a gate electrode of the seventh transistor is electricallyconnected with the reset control signal terminal, a first electrode ofthe seventh transistor is electrically connected with the third voltageterminal, and a second electrode of the seventh transistor iselectrically connected with the first electrode of the light-emittingelement.

For example, the pixel circuit provided by at least one embodiment ofthe present disclosure further comprises a storage sub-circuit, thestorage sub-circuit is electrically connected to the control terminal ofthe driving sub-circuit and the first voltage terminal, and isconfigured to store a compensation signal acquired based on the datasignal.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, the storage sub-circuit comprises a firstcapacitor, the data writing sub-circuit comprises a third transistor,and the driving sub-circuit comprises a fourth transistor, the controlterminal of the driving sub-circuit comprises a gate electrode of thefourth transistor, the first terminal of the driving sub-circuitcomprises a first electrode of the fourth transistor, and the secondterminal of the driving sub-circuit comprises a second electrode of thefourth transistor; a gate electrode of the second transistor iselectrically connected with the compensation control signal terminal, asecond electrode of the second transistor is electrically connected withthe second electrode of the fourth transistor, and a first electrode ofthe second transistor is electrically connected with the gate electrodeof the fourth transistor; a first end of the first capacitor iselectrically connected with the gate electrode of the fourth transistor,and a second end of the first capacitor is electrically connected withthe first voltage terminal; a gate electrode of the third transistor iselectrically connected with the first scan signal terminal, a firstelectrode of the third transistor is electrically connected with thedata signal terminal, and a second electrode of the third transistor iselectrically connected with the first electrode of the fourthtransistor.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, the first light-emitting control sub-circuitcomprises a fifth transistor, and the second light-emitting controlsub-circuit comprises a sixth transistor; a gate electrode of the fifthtransistor is electrically connected with the light-emitting signalcontrol terminal, a first electrode of the fifth transistor is connectedwith the first voltage terminal, and a second electrode of the fifthtransistor is electrically connected with the first terminal of thedriving sub-circuit; a gate electrode of the sixth transistor iselectrically connected with the light-emitting signal control terminal,a first electrode of the sixth transistor is electrically connected withthe second terminal of the driving sub-circuit, and a second electrodeof the sixth transistor is electrically connected with the firstelectrode of the light-emitting element.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, a gate electrode of the first transistor iselectrically connected with the second scan signal terminal, a firstelectrode of the first transistor is electrically connected with thesecond terminal of the driving sub-circuit, and a second electrode ofthe first transistor is electrically connected with the second voltageterminal.

For example, the pixel circuit provided by at least one embodiment ofthe present disclosure further comprises a storage sub-circuit and asecond reset sub-circuit, the storage sub-circuit comprises a firstcapacitor, the data writing sub-circuit comprises a third transistor,the driving sub-circuit comprises a fourth transistor, the firstlight-emitting control sub-circuit comprises a fifth transistor, thesecond light-emitting control sub-circuit comprises a sixth transistor,and the second reset sub-circuit comprises a seventh transistor; a gateelectrode of the first transistor is electrically connected with thesecond scan signal terminal, a first electrode of the first transistoris electrically connected with a second electrode of the fourthtransistor, and a second electrode of the first transistor iselectrically connected with the second voltage terminal; a gateelectrode of the second transistor is electrically connected with thecompensation control signal terminal, a first electrode of the secondtransistor is electrically connected with a gate electrode of the fourthtransistor, and a second electrode of the second transistor iselectrically connected with the second electrode of the fourthtransistor; a first end of the first capacitor is electrically connectedwith the gate electrode of the fourth transistor, and a second end ofthe first capacitor is electrically connected with the first voltageterminal; a gate electrode of the third transistor is electricallyconnected with the first scan signal terminal, a first electrode of thethird transistor is electrically connected with the data signalterminal, and a second electrode of the third transistor is electricallyconnected with a first electrode of the fourth transistor; a gateelectrode of the fifth transistor is electrically connected with thelight-emitting signal control terminal, a first electrode of the fifthtransistor is connected with the first voltage terminal, and a secondelectrode of the fifth transistor is electrically connected with thefirst electrode of the fourth transistor; a gate electrode of the sixthtransistor is connected with the light-emitting signal control terminal,a first electrode of the sixth transistor is electrically connected withthe second electrode of the fourth transistor, and a second electrode ofthe sixth transistor is electrically connected with the first electrodeof the light-emitting element; a gate electrode of the seventhtransistor is electrically connected with the reset control signalterminal, a first electrode of the seventh transistor is electricallyconnected with a third voltage terminal, and a second electrode of theseventh transistor is electrically connected with the second electrodeof the sixth transistor.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, the third transistor, the fourth transistor, thefifth transistor, the sixth transistor, and the seventh transistor arepolysilicon thin film transistors.

For example, in the pixel circuit provided by at least one embodiment ofthe present disclosure, the signal of the light-emitting signal controlterminal is not a pulse modulation signal, and the compensation controlsignal terminal and the light-emitting signal control terminal areconnected to an identical signal line.

At least one embodiment of the present disclosure provides a displaydevice, comprising a plurality of sub-pixels arranged in an array, eachsub-pixel comprises the pixel circuit and the light-emitting elementaccording to any embodiment of the present disclosure.

For example, in the display device provided by at least one embodimentof the present disclosure, second scan signal terminals of pixelcircuits of sub-pixels located in an i-th row and compensation controlsignal terminals of pixel circuits of sub-pixels located in an (i-1)-throw are connected to an identical signal line, where i is a positiveinteger greater than 1 and i is less than or equal to a total number ofrows of the plurality of sub-pixels.

At least one embodiment of the present disclosure provides a drivingmethod for driving the pixel circuit according to any embodiment of thepresent disclosure, a working process of the pixel circuit in onedisplay frame comprises an initialization phase, a data writing phase,and a light-emitting phase, the driving method comprises: in theinitialization phase, controlling a level of the signal of the firstscan signal terminal to be a first level, controlling a level of thesignal of the second scan signal terminal to be the first level,controlling a level of the signal of the compensation control signalterminal to be the first level, and controlling a level of the signal ofthe light-emitting signal control terminal to be the first level; in thedata writing phase, controlling the level of the signal of the firstscan signal terminal to be a second level, controlling the level of thesignal of the second scan signal terminal to be the second level,controlling the level of the signal of the compensation control signalterminal to be the first level, and controlling the level of the signalof the light-emitting signal control terminal to be the first level; inthe light-emitting phase, controlling the level of the signal of thefirst scan signal terminal to be the first level, controlling the levelof the signal of the second scan signal terminal to be the second level,controlling the level of the signal of the compensation control signalterminal to be the second level, and controlling the level of the signalof the light-emitting signal control terminal to be the second level.

For example, in the driving method for driving the pixel circuitprovided by at least one embodiment of the present disclosure, in a casewhere the pixel circuit comprises a second reset sub-circuit, the secondreset sub-circuit is configured to write a signal of a third voltageterminal into the first electrode of the light-emitting element inresponse to a signal of a reset control signal terminal to reset thefirst electrode of the light-emitting element, the driving methodfurther comprises: controlling the signal of the first scan signalterminal to be identical with the signal of the reset control signalterminal.

For example, in the driving method for driving the pixel circuitprovided by at least one embodiment of the present disclosure, theworking process of the pixel circuit in the one display frame furthercomprises a non-light-emitting phase, the driving method furthercomprises: in the non-light-emitting phase, controlling the level of thesignal of the light-emitting signal control terminal to be the firstlevel, controlling the level of the signal of the first scan signalterminal to be the first level, controlling the level of the signal ofthe second scan signal terminal to be the second level, and controllingthe level of the signal of the compensation control signal terminal tobe the second level.

For example, in the driving method for driving the pixel circuitprovided by at least one embodiment of the present disclosure, thesignal of the light-emitting signal control terminal is a pulse widthmodulation signal.

For example, in the driving method for driving the pixel circuitprovided by at least one embodiment of the present disclosure, in a casewhere the pixel circuit is in a first display mode, the working processof the pixel circuit in the one display frame further comprises a resetphase, the driving method further comprises: in the reset phase,controlling the level of the signal of the light-emitting signal controlterminal to be the first level, controlling the level of the signal ofthe first scan signal terminal to be the second level, controlling thelevel of the signal of the second scan signal terminal to be the secondlevel, and controlling the level of the signal of the compensationcontrol signal terminal to be the second level.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of theembodiments of the present disclosure, the drawings of the embodimentswill be briefly described in the following; it is obvious that thedescribed drawings are only related to some embodiments of the presentdisclosure and thus are not limitative to the present disclosure.

FIG. 1 is a schematic structural diagram of a pixel circuit;

FIG. 2 is a schematic structural diagram of a pixel circuit according toat least one embodiment of the present disclosure;

FIG. 3 is a schematic block diagram of a display device according to atleast one embodiment of the present disclosure;

FIG. 4A to FIG. 4C are circuit timing diagrams of a pixel circuitaccording to at least one embodiment of the present disclosure;

FIG. 4D is a circuit timing diagram of another pixel circuit accordingto at least one embodiment of the present disclosure; and

FIG. 5 is a schematic structural diagram of another pixel circuitprovided by at least one embodiment of the present disclosure.

DETAILED DESCRIPTION

In order to make objects, technical solutions, and advantages of theembodiments of the present disclosure more apparent, the technicalsolutions of the embodiments of the present disclosure will be describedin a clearly and fully understandable way in connection with thedrawings related to the embodiments of the present disclosure.Apparently, the described embodiments are just a part but not all of theembodiments of the present disclosure. Based on the describedembodiments of the present disclosure, those skilled in the art canobtain other embodiment(s), without any inventive work, which should bewithin the protection scope of the present disclosure.

Unless otherwise defined, all the technical and scientific terms used inthe present disclosure have the ordinary meanings as commonly understoodby one of ordinary skill in the art to which the present disclosurebelongs. The terms “first,” “second,” etc., which are used in thepresent disclosure, are not intended to indicate any sequence, amount,or importance, but distinguish various components. The terms “comprise,”“comprising,” “include,” “including,” etc., are intended to specify thatthe elements or the objects stated before these terms encompass theelements or the objects and equivalents thereof listed after theseterms, but do not preclude the other elements or objects. The phrases“connect”, “connected”, etc., are not intended to define a physicalconnection or mechanical connection, but may include an electricalconnection, directly or indirectly. “On,” “under,” “right,” “left” andthe like are only used to indicate relative position relationship, andwhen the position of the object which is described is changed, therelative position relationship may be changed accordingly. In order tokeep the following description of the embodiments of the presentdisclosure clear and concise, the present disclosure omits a detaileddescription of some well-known functions and well-known components.

In the embodiment of the present disclosure, a transistor refers to anelement including at least a gate electrode, a drain electrode, and asource electrode. The transistor has a channel between the drainelectrode (drain electrode terminal, drain region, or drain electrode)and the source electrode (source electrode terminal, source region, orsource electrode) of the transistor, and a current may flow through thedrain electrode, the channel, and the source electrode. It should benoted that, in the present disclosure, the channel refers to a part ofthe active layer corresponding to an orthographic projection of the gateelectrode of the transistor on the active layer, that is, the regionwhere the current mainly flows.

In the present disclosure, a first electrode may be a drain electrodeand a second electrode may be a source electrode, or the first electrodemay be a source electrode and the second electrode may be a drainelectrode. When transistors with opposite polarities are used or thecurrent direction changes during operation of the circuit, etc., thefunction of “the source electrode” and the function of “the drainelectrode” are sometimes interchanged with each other. In the embodimentof the present disclosure, in order to distinguish the transistors,except the gate electrode as the control electrode, one of the firstelectrode and the second electrode is directly described as the firstelectrode and the other of the first electrode and the second electrodeis directly described as the second electrode, so the first electrodeand the second electrode of all or part of the transistors in theembodiment of the present disclosure may be interchanged as needed.

In the present disclosure, “connection” includes the case whereconstituent components are connected together by an element having acertain electrical effect. The “element having a certain electricaleffect” is not particularly limited as long as it can transmit andreceive electrical signals between connected constituent components.Examples of “element having a certain electrical effect” include notonly electrodes and wirings, but also switching elements such astransistors, resistors, inductors, capacitors, other elements withvarious functions, and the like.

FIG. 1 is a schematic structural diagram of a pixel circuit. As shown inFIG. 1 , the pixel circuit includes seven transistors T1 to T7, a firstcapacitor Cst, and a light-emitting element OLED.

For the pixel circuit shown in FIG. 1 , the gate electrode of thedriving transistor T3 (i.e., P1 point in FIG. 1 ) has two leakage paths,that is, a first leakage path formed by the transistor T1 and a secondleakage path formed by the transistor T2. Because of the existence ofthe two leakage paths, the voltage leakage at the P1 point may be largerin the light-emitting phase of the light-emitting element OLED, and thenthe current flowing through the light-emitting element OLED becomessmaller, resulting in the problem of screen flickering.

At least one embodiment of that present disclosure provides a pixelcircuit including a driving sub-circuit, a data writing sub-circuit, afirst light-emitting control sub-circuit, a second light-emittingcontrol sub-circuit, a compensation sub-circuit, and a first resetsub-circuit, and the pixel circuit is configured to generate a drivingcurrent to control a light-emitting element to emit light. The firstreset sub-circuit includes a first transistor, the compensationsub-circuit includes a second transistor, the first transistor and thesecond transistor are polysilicon oxide thin film transistors, and anactive layer type of the first transistor and an active layer type ofthe second transistor are different from an active layer type of atransistor comprised in at least one selected from a group consisting ofthe driving sub-circuit, the data writing sub-circuit, the firstlight-emitting control sub-circuit, and the second light-emittingcontrol sub-circuit.

In the pixel circuit, by connecting the first reset sub-circuit with thesecond end of the driving sub-circuit, so that only one leakage pathexists at the control terminal of the driving sub-circuit. Because ofthe reduction of the leakage path, the voltage leakage at the controlterminal of the driving sub-circuit 122 is relatively small in thelight-emitting phase, and the difference in brightness before and aftera frame image is reduced, the flicker problem of the display screen isoptimized, and the uniformity of the display image and the displayquality of the display panel including the pixel circuit are improved.

Some embodiments of the present disclosure will be described in detailbelow with reference to the accompanying drawings, but the presentdisclosure is not limited to these specific embodiments.

FIG. 2 is a schematic structural diagram of a pixel circuit provided byat least one embodiment of the present disclosure.

As shown in FIG. 2 , the pixel circuit 121 includes a drivingsub-circuit 122, a data writing sub-circuit 123, a first light-emittingcontrol sub-circuit 124, a second light-emitting control sub-circuit125, a compensation sub-circuit 126, and a first reset sub-circuit 127.The pixel circuit 121 is configured to generate a driving current tocontrol the light-emitting element 120 to emit light.

For example, as shown in FIG. 2 , the light-emitting element 120includes a first electrode, a second electrode, and a light-emittinglayer disposed between the first electrode and the second electrode, andthe second electrode of the light-emitting element 120 is electricallyconnected to a fourth voltage terminal VSS. When the driving currentgenerated by the pixel circuit 121 flows through the light-emittingelement 120, the light-emitting layer of the light-emitting element 120emits light with brightness corresponding to the magnitude of thedriving current.

For example, the light-emitting element 120 may be a light-emittingdiode or the like. The light-emitting diode may be a micro lightemitting diode (Micro LED), an organic light emitting diode (OLED), aquantum dot light emitting diode (QLED), etc. The light-emitting element120 is configured to receive a light-emitting signal (for example, thelight-emitting signal may be a driving current) and emit light with anintensity corresponding to the light-emitting signal during operation.The first electrode of the light-emitting element 120 may be an anode,and the second electrode of the light-emitting diode may be a cathode.It should be noted that in the embodiment of the present disclosure, thelight-emitting layer of the light-emitting element may include anelectroluminescent layer itself and other common layers located on bothsides of the electroluminescent layer, for example, the other commonlayers may comprise a hole injection layer, a hole transport layer, anelectron injection layer, an electron transport layer, and so on.Generally, the light-emitting element 120 has a light-emitting thresholdvoltage and emits light when the voltage between the first electrode andthe second electrode of the light-emitting element 120 is greater thanor equal to the light-emitting threshold voltage. In practicalapplication, the specific structure of the light-emitting element 120may be designed and determined according to the actual applicationenvironment, which is not limited here.

For example, the driving sub-circuit 122 includes a control terminal, afirst terminal, and a second terminal, and is configured to provide thelight-emitting element 120 with a driving current for driving thelight-emitting element 120 to emit light. For example, the controlterminal of the driving sub-circuit 122 is electrically connected to afirst node N1, the first terminal of the driving sub-circuit 122 iselectrically connected to a second node N2, and the second terminal ofthe driving sub-circuit 122 is electrically connected to a third nodeN3.

For example, the data writing sub-circuit 123 is electrically connectedto the first terminal of the driving sub-circuit and the data signalterminal Vdata, and the data writing sub-circuit 123 is configured towrite the data signal of the data signal terminal Vdata into the firstterminal of the driving sub-circuit 122 in response to the signal of thefirst scan signal terminal Ga1.

For example, the compensation sub-circuit 126 is electrically connectedto the second terminal of the driving sub-circuit 122 and the controlterminal of the driving sub-circuit 122, and the compensationsub-circuit 126 is configured to perform threshold compensation on thedriving sub-circuit 122 in response to the signal of the compensationcontrol signal terminal Cps.

For example, the first light-emitting control sub-circuit 124 iselectrically connected to the first terminal of the driving sub-circuit122 and the first voltage terminal VDD, and the first light-emittingcontrol sub-circuit 124 is configured to achieve the connection betweenthe driving sub-circuit 122 and the first voltage terminal VDD to beturned on or off in response to the signal of the light-emitting signalcontrol terminal EM.

For example, the second light-emitting control sub-circuit 125 iselectrically connected to the second terminal of the driving sub-circuit122 and the first electrode of the light-emitting element 120, and thesecond light-emitting control sub-circuit 125 is configured to achievethe connection between the driving sub-circuit 122 and thelight-emitting element 120 to be turned on or off in response to thesignal of the light-emitting signal control terminal EM.

For example, the first reset sub-circuit 127 is electrically connectedto the second terminal of the driving sub-circuit 122 and the secondvoltage terminal Vinit1, and the first reset sub-circuit 127 isconfigured to write the signal of the second voltage terminal Vinit1into the second terminal of the driving sub-circuit 122 in response tothe signal of the second scan signal terminal Ga2 to initialize thesecond terminal of the driving sub-circuit 122.

For example, the first reset sub-circuit 127 includes a first transistorT1, the compensation sub-circuit 126 includes a second transistor T2,the first transistor T1 and the second transistor T2 are bothpolysilicon oxide thin film transistors, for example, the firsttransistor T1 and the second transistor T2 are low temperaturepolysilicon oxide (LTPO) thin film transistors.

Low temperature poly silicon (LTPS) process is the manufacturing processof a new generation of thin film transistor liquid crystal displays(TFT-LCDs). In the encapsulation process of the LTPS process, an excimerlaser is used as the heat source. After the laser passes through thetransmission system, laser beams with uniform energy distribution may begenerated and projected on the glass substrate with an amorphous siliconstructure. When the glass substrate with the amorphous silicon structureabsorbs the energy of the excimer laser, the glass substrate will betransformed into polysilicon structure. Because the whole process iscompleted below 500-600° C., which is lower than the temperature of morethan 1000° C. in the traditional polysilicon process, so it is called alow-temperature polysilicon process.

In the field of display technology, the low temperature polysilicon(LTPS) process and the oxide (for example, Indium Gallium Zinc Oxide(IGZO)) process are two processes commonly used to manufacture thin filmtransistor (TFT) array substrates. LTPO process combines thelow-temperature polysilicon process and the oxide process to maximizethe advantages of ultra-high mobility of low-temperature polysilicon andsmall leakage current of oxides (such as indium gallium zinc oxide),thereby achieving better display performance.

For example, an active layer type of the first transistor T1 and anactive layer type of the second transistor T2 are different from anactive layer type of a transistor comprised in at least one selectedfrom a group consisting of the driving sub-circuit 122, the data writingsub-circuit 123, the first light-emitting control sub-circuit 124, andthe second light-emitting control sub-circuit 125, that is, the pixelcircuit is a pixel circuit with a plurality of transistor types.

It should be noted that, in the present disclosure, “active layer type”indicates the type of the material used for manufacturing the activelayer, and the material of the active layer may include indium galliumzinc oxide, low-temperature polysilicon, amorphous silicon (such ashydrogenated amorphous silicon), low-temperature polysilicon oxide, etc.For example, the active layer type of a thin film transistor usingindium gallium zinc oxide as the active layer is different from theactive layer type of a thin film transistor using low-temperaturepolysilicon oxide as the active layer.

In the pixel circuit 121, the first reset sub-circuit 127 is connectedwith the second terminal of the driving sub-circuit 122, so that onlyone leakage path exists at the control terminal of the drivingsub-circuit 122 (that is, the compensation sub-circuit 126 connectedwith the control terminal of the driving sub-circuit 122). Because ofthe reduction of the leakage path, in the light-emitting phase, thevoltage leakage of the control terminal of the driving sub-circuit 122is less, the difference in brightness of a frame image is reduced, theproblem of flicker is optimized, the uniformity of the displayed imageis improved, and the display quality of the display panel including thepixel circuit is improved.

For example, as shown in FIG. 2 , the pixel circuit 121 may furtherinclude a second reset sub-circuit 129, the second reset sub-circuit 129is electrically connected with the first electrode of the light-emittingelement 120 and the third voltage terminal Vinit2, and the second resetsub-circuit 129 is configured to write the signal of the third voltageterminal Vinit2 into the first electrode of the light-emitting element120 in response to the signal of the reset control signal terminal Rstto reset the first electrode of the light-emitting element 120.

For example, the first scan signal terminal Ga1 and the reset controlsignal terminal Rst may be connected to the same signal line to reduce agroup of GOA(Gate Driver on Array) signals, which is beneficial to thenarrow frame design of the display panel, reduces the wiring space ofthe pixel circuit, and improves the resolution of the display panel. Inthis case, the first scan signal terminal Ga1 and the reset controlsignal terminal Rst may be the same signal terminal, that is, one signalterminal, such as the reset control signal terminal Rst, may be omitted.In this case, the second reset sub-circuit 129 is configured to writethe signal of the third voltage terminal Vinit2 into the first electrodeof the light-emitting element 120 in response to the signal of the firstscan signal terminal Ga1, so as to reset the first electrode of thelight-emitting element 120.

For example, the display panel often has a case of a low image switchingfrequency such as switching picture display, web browsing, etc. Forexample, at this time, the switching frequency of images is 5 Hz, andthe pixel circuit is in the first display mode, that is, a low-frequencydisplay mode. When the display panel displays the dynamic video or thelike, the image switching frequency is relatively high, for example, theswitching frequency of the images is 50 Hz at this time, and the pixelcircuit is in the second display mode, that is, a high-frequency displaymode. Therefore, compared with the second display mode, in the firstdisplay mode, the frequency of writing the data signal into the controlterminal of the driving sub-circuit 122 is correspondingly reduced.However, in order to avoid the flicker problem, it is usually necessaryto keep the first electrode of the light-emitting element 120 in thestate of high-frequency reset, that is, the frequency of the signal atthe reset control signal terminal Rst in the first display mode remainsthe same as the frequency of the signal at the reset control signalterminal Rst in the second display mode.

In order to reduce the wiring space of the pixel circuit, the first scansignal terminal Ga1 and the reset control signal terminal Rst may beconnected to the same signal line, so that in the first display mode,the frequency of the signal at the first scan signal terminal Ga1remains the same as the frequency of the signal at the first scan signalterminal Ga1 in the second display mode.

For example, the data writing sub-circuit 123 includes a thirdtransistor T3. When the pixel circuit 121 is in the first display mode,the turn-on frequency of the third transistor T3 included in the datawriting sub-circuit 123 is greater than the turn-on frequency of thesecond transistor T2 included in the threshold compensation sub-circuit,and only when the third transistor T3 and the second transistor T2 areboth turned on, the data signal is transmitted to the control terminalof the driving sub-circuit 122. Because writing the data signal to thecontrol terminal of the driving sub-circuit 122 is determined by theturn-on frequency of the second transistor T2, the frequency of thesignal at the compensation control signal terminal of the secondtransistor T2 is reduced according to the display demand of the firstdisplay mode, so as to achieve the low-frequency writing of the datasignal and the low-frequency display.

It should be noted that the turn-on frequency here refers to the numberof times a transistor is turned on per unit time. For example, thehigher the frequency of the control signal of the gate electrode of thetransistor, the higher the turn-on frequency of the transistor.

For example, the voltage value of the signal at the third voltageterminal Vinit2 is greater than that of the signal at the second voltageterminal Vinit1. By increasing the voltage value at the third voltageterminal Vinit2, the carriers in the light-emitting element 120 arereset, the defects of carriers are reduced, the device stability isincreased, and the screen flicker problem is further ameliorated.

For example, the voltage range of the second voltage terminal Vinit1 maybe −2V (volts)˜−6V, for example, the voltage of the second voltageterminal Vinit1 may be −5V, and the voltage range of the third voltageterminal Vinit2 may be −2V˜−5V, for example, the voltage of the thirdvoltage terminal Vinit2 may be −3V.

For example, as shown in FIG. 2 , the second reset sub-circuit 129includes a seventh transistor T7, a gate electrode of the seventhtransistor T7 is electrically connected to the reset control signalterminal Rst, a first electrode of the seventh transistor T7 iselectrically connected to the third voltage terminal Vinit2, and asecond electrode of the seventh transistor T7 is electrically connectedto the first electrode of the light-emitting element 120.

For example, the channel width of the seventh transistor T7 ranges from1.5 μm to 3 μm, the channel length of the seventh transistor T7 rangesfrom 2 μm to 4 μm, the channel width of the first transistor T1 rangesfrom 1.5 gm to 3 μm, and the channel length of the first transistor T1ranges from 2 μm to 4 μm.

For example, the channel length of the first transistor T1 is greaterthan the channel length of the seventh transistor T7, and the channellength of the sixth transistor T6 is greater than or equal to thechannel length of the seventh transistor T7 and less than the channellength of the first transistor T1. Therefore, for the leakage pathsexisting at the gate electrode of the fourth transistor T4, such as theleakage path 1 to the second voltage terminal Vinit1 through the secondtransistor T2 and the first transistor T1, and the leakage path 2 to thethird voltage terminal Vinit2 through the second transistor T2, thesixth transistor T6, and the seventh transistor T7, by setting thechannel length relationship among the first transistor T1, the sixthtransistor T6, and the seventh transistor T7, the leakage problem can befurther alleviated and the display effect can be improved.

For example, the ratio of the channel length of the first transistor T1to the channel length of the seventh transistor T7 may be 1 to 2, suchas 1.1, 1.3, 1.5, 1.7, and 1.9; the ratio of the channel length of thefirst transistor T1 to the channel length of the sixth transistor T6 maybe 1 to 2, for example, 1.1, 1.3, 1.5, 1.7, and 1.9.

For example, as shown in FIG. 2 , the pixel circuit 121 may furtherinclude a storage sub-circuit 128, the storage sub-circuit 128 iselectrically connected to the control terminal of the drivingsub-circuit 122 and the first voltage terminal VDD, and the storagesub-circuit 128 is configured to store a compensation signal acquiredbased on the data signal.

For example, as shown in FIG. 2 , the driving sub-circuit 122 includesthe fourth transistor T4, the control terminal of the drivingsub-circuit 122 includes the gate electrode of the fourth transistor T4,the first terminal of the driving sub-circuit 122 includes the firstelectrode of the fourth transistor T4, and the second terminal of thedriving sub-circuit 122 includes the second electrode of the fourthtransistor T4.

For example, as shown in FIG. 2 , the data writing sub-circuit 123includes a third transistor T3, the gate electrode of the thirdtransistor T3 is electrically connected to the first scan signalterminal Ga1, the first electrode of the third transistor T3 iselectrically connected to the data signal terminal Vdata, and the secondelectrode of the third transistor T3 is electrically connected to thefirst electrode of the fourth transistor T4, that is, the secondelectrode of the third transistor T3 is electrically connected to thesecond node N2.

For example, as shown in FIG. 2 , the compensation sub-circuit 126includes a second transistor T2, the gate electrode of the secondtransistor T2 is electrically connected to the compensation controlsignal terminal Cps, the second electrode of the second transistor T2 iselectrically connected to the second electrode of the fourth transistorT4, that is, the second electrode of the second transistor T2 iselectrically connected to the third node N3, and the first electrode ofthe second transistor T2 is electrically connected to the gate electrodeof the fourth transistor T4, that is, the first electrode of the secondtransistor T2 is electrically connected to the first node N1.

For example, as shown in FIG. 2 , the storage sub-circuit 128 includes afirst capacitor Cst, the first end of the first capacitor Cst iselectrically connected to the gate electrode of the fourth transistorT4, that is, the first end of the first capacitor Cst is electricallyconnected to the first node N1, and the second end of the firstcapacitor Cst is electrically connected to the first voltage terminalVDD.

For example, as shown in FIG. 2 , the first light-emitting controlsub-circuit 124 includes a fifth transistor T5, and the secondlight-emitting control sub-circuit 125 includes a sixth transistor T6.For example, the gate electrode of the fifth transistor T5 iselectrically connected to the light-emitting signal control terminal EM,the first electrode of the fifth transistor T5 is connected to the firstvoltage terminal VDD, and the second electrode of the fifth transistorT5 is electrically connected to the first terminal of the drivingsub-circuit 122, that is, the second electrode of the fifth transistorT5 is electrically connected to the second node N2; the gate electrodeof the sixth transistor T6 is electrically connected to thelight-emitting signal control terminal EM, the first electrode of thesixth transistor T6 is electrically connected to the second terminal ofthe driving sub-circuit 122, that is, the first electrode of the sixthtransistor T6 is electrically connected to the third node N3, and thesecond electrode of the sixth transistor T6 is electrically connected tothe first electrode of the light-emitting element 120.

For example, as shown in FIG. 2 , the gate electrode of the firsttransistor T1 is electrically connected to the second scan signalterminal Ga2, the first electrode of the first transistor T1 iselectrically connected to the second terminal of the driving sub-circuit122, that is, the gate electrode of the first transistor T1 iselectrically connected to the third node N3, and the second electrode ofthe first transistor T1 is electrically connected to the second voltageterminal Vinit1.

For example, when the signal of the light-emitting signal controlterminal EM is not a pulse width modulation signal, that is, the signalof the light-emitting signal control terminal EM is a pulse signal witha fixed duty cycle, the compensation control signal terminal Cps and thelight-emitting signal control terminal EM may be connected to the samesignal line. At this time, under the control of the signal at thelight-emitting signal control terminal EM, before the third transistorT3 is turned on, the second transistor T2 is already turned on, thusreducing the waste of turn-on time of one transistor when the datasignal is written, reducing the loss of charging time caused by therising edge of the signal at the control terminal not reaching a turn-onlevel immediately, increasing the charging time, which is more conduciveto the image display in the high-frequency display mode.

For example, taking FIG. 2 as an example, the connection relationshipamong the transistor T1 to the transistor T7, the first capacitor Cst,and the respective signal control terminals will be described in detailbelow.

For example, the storage sub-circuit 128 of the pixel circuit includesthe first capacitor Cst, the data writing sub-circuit 123 includes thethird transistor T3, the driving sub-circuit 122 includes the fourthtransistor T4, the first light-emitting control sub-circuit 124 includesthe fifth transistor T5, the second light-emitting control sub-circuit125 includes the sixth transistor T6, and the second reset sub-circuit129 includes the seventh transistor T7.

The gate electrode of the first transistor T1 is electrically connectedwith the second scan signal terminal Ga2, the first electrode of thefirst transistor T1 is electrically connected with the second electrodeof the fourth transistor T4, and the second electrode of the firsttransistor T1 is electrically connected with the second voltage terminalVinit1; the gate electrode of the second transistor T2 is electricallyconnected with the compensation control signal terminal Cps, the firstelectrode of the second transistor T2 is electrically connected with thegate electrode of the fourth transistor T4, and the second electrode ofthe second transistor T2 is electrically connected with the secondelectrode of the fourth transistor T4; the first end of the firstcapacitor Cst is electrically connected with the gate electrode of thefourth transistor T4, and the second end of the first capacitor Cst iselectrically connected with the first voltage terminal VDD; the gateelectrode of the third transistor T3 is electrically connected with thefirst scan signal terminal Ga1, the first electrode of the thirdtransistor T3 is electrically connected with the data signal terminalVdata, and the second electrode of the third transistor T3 iselectrically connected with the first electrode of the fourth transistorT4; the gate electrode of the fifth transistor T5 is electricallyconnected with the light-emitting control signal terminal EM, the firstelectrode of the fifth transistor T5 is electrically connected with thefirst voltage terminal Vinit1, and the second electrode of the fifthtransistor T5 is electrically connected with the first electrode of thefourth transistor T4; the gate electrode of the sixth transistor T6 isconnected to the light-emitting signal control terminal EM, the firstelectrode of the sixth transistor T6 is electrically connected to thesecond electrode of the fourth transistor T4, and the second electrodeof the sixth transistor T6 is electrically connected to the firstelectrode of the light-emitting element 120; the gate electrode of theseventh transistor T7 is electrically connected with the reset controlsignal terminal Rst, the first electrode of the seventh transistor T7 iselectrically connected with the third voltage terminal Vinit2, and thesecond electrode of the seventh transistor T7 is electrically connectedwith the second electrode of the sixth transistor T6.

For example, a plurality of pixel circuits 121 and a plurality oflight-emitting elements 120 shown in FIG. 2 constitute a plurality ofsub-pixels, and the plurality of sub-pixels are arranged in an array.For a pixel circuit located in an n-th row, the signal of the secondscan signal terminal of the pixel circuit is the same as the signal ofthe compensation control signal terminal Cps of a pixel circuit locatedin a (n−1)-th row, that is, the second scan signal terminal of the pixelcircuit located in the n-th row and the compensation control signalterminal Cps of the pixel circuit located in the (n−1)-th row areconnected to the same signal line to receive the same signal, therebyreducing the number of signal lines.

For example, the third transistor T3 to the seventh transistor T7 areall polysilicon thin film transistors, such as low temperaturepolysilicon (LTPS) thin film transistors.

In this embodiment, compared with the LTPS thin film transistor, theLTPO thin film transistor generates less leakage current. Therefore,setting the second transistor T2 as LTPO thin film transistor cansignificantly reduce the leakage current.

For example, one of the voltage output from the first voltage terminalVDD and the voltage output from the fourth voltage terminal VSS is ahigh voltage, and the other is a low voltage. For example, in theembodiment shown in FIG. 2 , the voltage output from the first voltageterminal VDD is a constant first voltage VDD, for example, the firstvoltage is a positive voltage; while the voltage output from the fourthvoltage terminal VSS is a constant second voltage VS, for example, thesecond voltage is a negative voltage, etc. For example, in someexamples, the fourth voltage terminal VSS may be grounded.

For example, in the specific implementation, in the embodiment of thepresent disclosure, the voltage Vi output from the third voltageterminal Vinit2 and the second voltage Vs output from the fourth voltageterminal VSS may satisfy the following formula: Vi-Vs<VEL, so that thelight-emitting element 120 can be prevented from emitting light in thenon-light-emitting phase (for example, the initialization phase s1 to bedescribed below, etc.). VEL represents the light-emitting thresholdvoltage of the light-emitting element 120.

For example, according to the characteristics of the transistor, thetransistors may be divided into N-type transistors and P-typetransistors. For the sake of clarity, the embodiment of the presentdisclosure elaborates the technical solution of the present disclosurein detail by taking a case that the first transistor and the secondtransistor are N-type transistors (for example, N-type MOS transistors),and other transistors included in the pixel circuit are all P-typetransistors (for example, P-type MOS transistors) as an example. That isto say, in the description of the present disclosure, the firsttransistor T1 and the second transistor T2 are LTPO thin filmtransistors, such as, N-type transistors, and the third transistor T3 tothe seventh transistor T7 may be LTPS transistors, such as, P-typetransistors. However, the transistors in the embodiments of the presentdisclosure are not limited to this, and those skilled in the art mayalso use P-type transistors as the first transistor T1 and the secondtransistor T2 and use N-type transistors as the third transistor T3 tothe seventh transistor T7 according to the actual applicationenvironment, and the present disclosure is not limited thereto.

FIG. 3 is a schematic block diagram of a display device provided by atleast one embodiment of the present disclosure.

For example, the display device 10 may be an active-matrix organic lightemitting diode (AMOLED) display device or the like.

As shown in FIG. 3 , the display device 10 includes a display panel1000, a gate driver 1010, a timing controller 1020, and a data driver1030. The display panel 1000 includes sub-pixels P defined according tothe intersection of a plurality of scan lines GL and a plurality of datalines DL; the gate driver 1010 is used to drive the plurality of scanlines GL; the data driver 1030 is used to drive the plurality of datalines DL; the timing controller 1020 is used to process the image dataRGB input from the outside of the display device 10, provide theprocessed image data RGB to the data driver 1030, and output the scancontrol signal GCS and the data control signal DCS to the gate driver1010 and the data driver 1030 to control the gate driver 1010 and thedata driver 1030.

For example, the display panel 1000 may include a base substrate (notshown), and a plurality of sub-pixels P arranged in an array andincluded in the display device 10 are disposed on the base substrate,each sub-pixel P includes a light-emitting element 120 and a pixelcircuit 121. For example, the pixel circuit 121 may be the pixel circuitprovided by any embodiment of the present disclosure as mentioned above,and details will not be repeated here.

For example, the base substrate may be a flexible substrate or a rigidsubstrate. For example, the base substrate may be made of glass,plastic, quartz, or other suitable materials, and the embodiments of thepresent disclosure do not limit this.

For example, on the base substrate, the light-emitting element 120 andthe pixel circuit 121 are stacked, and the light-emitting element 120 islocated on the side of the pixel circuit 121 away from the basesubstrate 10. The pixel circuit 121 is configured to drive thelight-emitting element 120 to emit light.

As shown in FIG. 3 , the display panel 1000 further includes theplurality of scan lines GL and the plurality of data lines DL. Forexample, the sub-pixel P is disposed at the intersection region of thescan line GL and the data line DL. For example, each sub-pixel P isconnected to four scan lines GL (the first scan terminal Ga1, the secondscan terminal Ga2, the compensation control signal terminal Cps, and thereset control signal terminal Rst, respectively), a data line DL, afirst voltage terminal for providing the first voltage VDD, a secondvoltage terminal for providing the first initial voltage Vinit1, a thirdvoltage terminal for providing the second initial voltage Vinit2, and afourth voltage terminal VSS for providing the second voltage. Forexample, the first voltage terminal to the fourth voltage terminal maybe provided with voltages by corresponding power lines (for example,provided by a power management chip) or may be correspondingplate-shaped common electrodes (for example, common anode or commoncathode). It should be noted that only part of the sub-pixels P, part ofthe scan lines GL, and part of the data lines DL are shown in FIG. 3 .

For example, the second scan signal terminals of the pixel circuits ofthe sub-pixels located in the i-th row and the compensation controlsignal terminals of the pixel circuits of the sub-pixels located in the(i−1)-th row are connected to the same signal line, here i is a positiveinteger greater than 1 and i is less than or equal to the total numberof rows of the plurality of sub-pixels.

For example, for the pixel circuit of the sub-pixel located in the i-throw, the signal of the compensation control signal terminal Cps of thepixel circuit is Cps[i], and the signal of the second scan signalterminal Ga2 of the pixel circuit is Cps [i-1], that is, the signal ofthe compensation control signal terminal of the sub-pixel located in the(i−1)-th row.

The second scan signal terminal Ga2 and the compensation control signalterminal Cps are connected to the same signal line, which reduces thenumber of signal lines in the display device 10, reduces the wiringspace of pixel circuits, and achieves the narrow frame design of thedisplay device 10.

For example, the gate driver 1010 provides a plurality of gate signalsto the plurality of scan lines GL according to a plurality of scancontrol signals GCS from the timing controller 1020. The plurality ofgate signals include scan signals, reset signals, and the like. Thesesignals are supplied to each sub-pixel P through the plurality of scanlines GL.

For example, the data driver 1030, using the reference gamma voltage,converts the digital image data RGB input from the timing controller1020 into data signals according to a plurality of data control signalsDCS from the timing controller 1020. The data driver 1030 supplies theconverted data signals to the plurality of data lines DL.

For example, the timing controller 1020 processes externally inputtedimage data RGB to match the size and resolution of the display panel1000, and then provides the processed image data to the data driver1030. The timing controller 1020 generates a plurality of scan controlsignals GCS and a plurality of data control signals DCS usingsynchronization signals (such as, the dot clock DCLK, the data enablesignal DE, the horizontal synchronization signal Hsync, and the verticalsynchronization signal Vsync) input from the outside of the displaydevice 10. The timing controller 1020 provides the generated scancontrol signal GCS and the generated data control signal DCS to the gatedriver 1010 and the data driver 1030, respectively, for the control ofthe gate driver 1010 and the data driver 1030.

For example, the data driver 1030 may be connected with a plurality ofdata lines DL to provide data signals.

For example, the gate driver 1010 and the data driver 1030 may beimplemented as semiconductor chips. The display device 10 may alsoinclude other components, such as a signal decoding circuit, a voltageconversion circuit, etc. These components may be, for example,conventional components, which will not be described in detail here.

For example, the display device 10 may be applied to any products orcomponents with a display function, such as an e-book, a mobile phone, atablet computer, a television, a monitor, a notebook computer, a digitalphoto frame, a navigator, etc.

Regarding the technical effects of the display device 10 provided in theabove embodiments, reference may be made to the technical effects of thepixel circuit provided in the embodiments of the present disclosure, andsimilar portions will not be repeated here.

At least one embodiment of the present disclosure also provides adriving method of the pixel circuit, and the driving method is used todrive the pixel circuit provided according to any embodiment of thepresent disclosure.

FIGS. 4A to 4C are circuit timing diagrams of a pixel circuit providedby some embodiments of the present disclosure.

Next, the working process of the pixel circuit in one display frame willbe described in detail by taking a case that the first transistor T1 andthe second transistor T2 are N-type transistors (LTPO thin filmtransistors) and the third transistor T3 to the seventh transistor T7are P-type transistors (such as LTPS thin film transistors) in the pixelcircuit provided by the embodiment of the present disclosure as anexample and in combination with the pixel circuit shown in FIG. 2 andthe working timing diagrams shown in FIG. 4A to FIG. 4C.

As shown in FIG. 2 , the pixel circuit provided by the embodiment of thepresent disclosure includes seven transistors (the first transistor T1to the seventh transistor T7), a storage capacitor (the first capacitorCst), and five power supply terminals (the first voltage terminal VDD,the second voltage terminal Vinit1, the third voltage terminal Vinit2,the fourth voltage terminal VSS, and the data signal terminal Vdata).For example, the first voltage terminal VDD continuously provides ahigh-level first voltage VDD, and the fourth voltage terminal VSScontinuously provides a low-level second voltage Vs.

For example, as shown in FIG. 4A, EM represents the signal (hereinafterreferred to as a light-emitting control signal) of light-emitting signalcontrol terminal EM, Ga1 represents the signal (hereinafter referred toas a first scan signal) of the first scan signal terminal Ga1, Ga2represents the signal (hereinafter referred to as a second scan signal)of the second scan signal terminal Ga2, and Cps represents the signal(hereinafter referred to as a compensation control signal) of thecompensation control signal terminal Cps. It should be noted that, inthe embodiment of the present disclosure, reference numerals EM, Ga1,Ga2, and Cps indicate both the signal terminal and the signal of thesignal terminal.

For example, when the pixel circuit 121 includes the second resetsub-circuit 129, the signal of the first scan signal terminal Ga1 iscontrolled to be the same as the signal of the reset control signalterminal Rst. For example, the first scan signal terminal Ga1 and thereset control signal terminal Rst are connected to the same signal line.For example, the circuit timing of the reset control signal Rst outputfrom the reset control signal terminal Rst is the circuit timing of thefirst scan signal Ga1 shown in FIG. 4A to FIG. 4C.

For example, in the following description, the first level represents ahigh level and the second level represents a low level.

For example, as shown in FIG. 4A, the working process of a pixel circuitin a display frame may include an initialization phase s1, a datawriting phase s2, and a light-emitting phase s3. That is, the drivingmethod includes the initialization phase s1, the data writing phase s2,and the light-emitting phase s3.

In the initialization phase s1, controlling a level of the signal of thefirst scan signal terminal Ga1 to be a first level, controlling a levelof the signal of the second scan signal terminal Ga2 to be the firstlevel, controlling a level of the signal of the compensation controlsignal terminal Cps to be the first level, and controlling a level ofthe signal of the light-emitting signal control terminal EM to be thefirst level. That is to say, the first scan signal Ga1, the resetcontrol signal Rst, the second scan signal Ga2, the compensation controlsignal Cps, and the light-emitting signal control EM are all at the highlevel.

Therefore, in the initialization phase s1, the first transistor T1 isturned on under the control of the high level of the second scan signalGa2, and the second transistor T2 is also turned on under the control ofthe high level of the compensation control signal terminal Cps, so thatthe first initial voltage Vi1 output from the second voltage terminalVinit1 may be supplied to the gate electrode of the fourth transistorT4, that is, the first node N1, through the turned-on first transistort1 and the turned-on second transistor T2. Therefore, the voltage of thegate electrode of the fourth transistor T4 is the first initial voltageVi1, and the initialization of the gate electrode of the fourthtransistor T4 is implemented. The third transistor T3 is turned offunder the control of the high level of the first scan signal Ga1, thefifth transistor T5 is turned off under the control of the high level ofthe light-emitting control signal EM, the sixth transistor T6 is turnedoff under the control of the high level of the light-emitting controlsignal EM, and the seventh transistor T7 is turned off under the controlof the high level of the reset control signal Rst.

In the data writing phase s2, controlling the level of the signal of thefirst scan signal terminal Ga1 to be a second level, controlling thelevel of the signal of the second scan signal terminal Ga2 to be thesecond level, controlling the level of the signal of the compensationcontrol signal terminal Cps to be the first level, and controlling thelevel of the signal of the light-emitting signal control terminal EM tobe the first level. That is to say, the first scan signal Ga1, the resetcontrol signal Rst, and the second scan signal Ga2 are at the low level,and the compensation control signal Cps and the light-emitting controlsignal EM are at the high level.

Therefore, in the data writing phase s2, the third transistor T3 isturned on under the control of the low level of the first scan signalGa1 to provide the data voltage Vda on the data signal terminal Vdata tothe first electrode of the fourth transistor T4, that is, the secondnode N2, so that the voltage of the first electrode of the fourthtransistor T4 is the data voltage Vda. The second transistor T2 isturned on under the control of the high level of the compensationcontrol signal Cps, so that the fourth transistor T4 may be at a diodeconnection mode, and therefore, the voltage Vda of the first electrodeof the fourth transistor T4 charges the gate electrode of the fourthtransistor T4 until the voltage of the gate electrode of the fourthtransistor T4 is Vda+Vth, and the voltage Vda+Vth of the gate electrodeof the fourth transistor T4 is stored by the first capacitor Cst. At thesame time, the seventh transistor T7 is turned on under the control ofthe low level of the reset control signal Rst, so that the secondinitial voltage Vi2 output from the third voltage terminal Vinit2 may beprovided to the first electrode of the light-emitting element 121through the turned-on seventh transistor T7 to reset the first electrodeof the light-emitting element 121. The first transistor T1 is turned offunder the control of the low level of the second scan signal terminalGa2, the fifth transistor T5 is turned off under the control of the highlevel of the light-emitting control signal EM, and the sixth transistorT6 is turned off under the control of the high level of thelight-emitting control signal EM.

In the light-emitting phase s3, controlling the level of the signal ofthe first scan signal terminal Ga1 to be the first level, controllingthe level of the signal of the second scan signal terminal Ga2 to be thesecond level, controlling the level of the signal of the compensationcontrol signal terminal Cps to be the second level, and controlling thelevel of the signal of the light-emitting signal control terminal EM tobe the second level. That is to say, the first scan signal Ga1 and thereset control signal Rst are at the high level, and the second scansignal Ga2, the compensation control signal Cps, and the light-emittingcontrol signal EM are all at the low level.

Therefore, the fifth transistor T5 is turned on under the control of thelow level of the light-emitting control signal EM, so that the fifthtransistor T5 may provide the first voltage VDD output from the firstvoltage terminal VDD to the first electrode of the fourth transistor T4,and thus the voltage of the first electrode of the fourth transistor T4is the first voltage VDD. At this time, the voltage of the firstelectrode of the fourth transistor T4 is the first voltage VDD, andbased on the holding effect of the first capacitor Cst, the voltage ofthe gate electrode of the fourth transistor T4 is Vda+Vth, so that thefourth transistor T4 may be in a saturated state, so that the fourthtransistor T4 generates the driving current Ids:Ids=K*((Vda+Vth−VDD)-Vth)2=K*(Vda−VDD)², K is a structural constantrelated to the process and the design. The sixth transistor T6 is turnedon under the control of the low level of the light-emitting controlsignal EM, so that the sixth transistor T6 may conduct the secondelectrode of the fourth transistor T4 with the first electrode of thelight-emitting element 120, so that the driving current Ids flows intothe light-emitting element 120 to drive the light-emitting element 120to emit light. The first transistor T1 is turned off under the controlof the low level of the second scan signal Ga2, the second transistor T2is turned off under the control of the low level of the compensationcontrol signal Cps, the third transistor T3 is turned off under thecontrol of the high level of the first scan signal Ga1, and the seventhtransistor T7 is turned off under the control of the high level of thereset control signal Rst.

For example, through the above-mentioned initialization phase, datawriting phase, and light-emitting phase, the pixel circuit completes therefresh and display of the data signals. In order to maintain thestability of the displayed image, the working process of the pixelcircuit in one display frame may also include a non-light-emitting phases4 and a light-emitting phase s3 as shown in FIG. 4B. At this time, thedata signal is no longer refreshed, and the image corresponding to thecurrent data signal is maintained to display.

For example, the driving method further includes a non-light-emittingphase s4. In the non-light-emitting phase s4, controlling the level ofthe signal of the first scan signal terminal Ga1 to be the first level,controlling the level of the signal of the second scan signal terminalGa2 to be the second level, controlling the level of the signal of thecompensation control signal terminal Cps to be the second level, andcontrolling the level of the signal of the light-emitting signal controlterminal EM to be the first level. That is to say, the first scan signalGa1, the reset control signal Rst, and the light-emitting control signalEM are all at the high level, and the second scan signal Ga2 and thecompensation control signal Cps are at the low level.

Therefore, in the non-light-emitting phase s4, the first transistor T1is turned off under the control of the low level of the second scansignal Ga2, the second transistor T2 is turned off under the control ofthe low level of the compensation control signal Cps, the thirdtransistor T3 is turned off under the control of the high level of thefirst scan signal Ga1, the fifth transistor T5 is turned off under thecontrol of the high level of the light-emitting control signal EM, thesixth transistor T6 is turned off under the control of the high level ofthe light-emitting control signal EM, and the seventh transistor T7 isturned off under the control of the high level of the reset controlsignal Rst. That is to say, in the non-light-emitting phase s4, thefirst transistor T1 to the third transistor T3 and the fifth transistorT5 to the seventh transistor T7 in the pixel circuit are all turned off.Because of the storage function of the first capacitor Cst, the fourthtransistor T4 is still in the saturated state in the light-emittingphase s3.

The process of the light-emitting phase s3 after the non-light-emittingphase s4 is the same as that of the above-mentioned light-emitting phases3. Both the fifth transistor T5 and the sixth transistor T6 are turnedon under the control of the low level of the light-emitting controlsignal EM, so that the driving current Ids flows into the light-emittingelement 120 to drive the light-emitting element 120 to emit light, andthe detailed process will not be described again.

For example, as shown in FIG. 4C, the display screen includes aplurality of display frames. In the second display mode, the pluralityof display frames may be a display frame frame1, a display frame frame2,etc. as shown in FIG. 4C. In the chronological order, each display frameincludes the following phases: the initialization phase s1, the datawriting phase s2, the light-emitting phase s3, the non-light-emittingphase s4, and the light-emitting phase s3. For the display frame frame2,the phase division and phase composition are exactly the same as thoseof the display frame frame1, and FIG. 4C does not show the division ofthe various phases of the display frame frame2.

For example, taking the signal period of the light-emitting controlsignal EM as the criterion, in the second display mode, each displayframe includes two signal periods, and in the first signal period, thedata signal is refreshed through the initialization phase s1, the datawriting phase s2, and the light-emitting phase s3; in the second signalperiod, the maintenance of the data signal and the display of the imagecorresponding to the data signal are completed through thenon-light-emitting phase s4 and the light-emitting phase s3.

It should be noted that the schematic diagram of the display frameprovided by the present disclosure is only exemplary, and can beadjusted according to actual needs, for example, more or less signalperiods may be provided to achieve the matching between the frequency ofthe light-emitting control signal and the refresh frequency of thedisplay frame, and the present disclosure does not limit this.

In order to ensure the driving ability of the thin film transistor inlow gray scale display, the circuit may use the PWM signal for dimmingto ensure the display quality. For example, the signal of thelight-emitting signal control terminal EM may be a pulse widthmodulation (PWM) signal, that is, the duty cycle of the pulse of thesignal of the light-emitting signal control terminal EM may be modulatedaccording to the design requirement.

When the signal of the light-emitting control signal terminal EM is aPWM signal, the circuit timing diagram shown in FIG. 4A to FIG. 4C maystill be adopted. By adjusting the ratio of the low level/high leveltime of the PWM signal to the signal period, dimming is implemented toimprove the image quality of the display picture.

For example, in the first display mode, as mentioned above, in order toreduce the wiring space of the pixel circuit, the first scan signalterminal Ga1 and the reset control signal terminal Rst may be connectedto the same signal line, so that the frequency of the signal at thefirst scan signal terminal Ga1 remains the same as the frequency of thesignal at the first scan signal terminal Ga1 in the second display mode.

When both the second transistor T2 and the third transistor T3 areturned on, the data signal can be transmitted to the gate electrode ofthe fourth transistor T4. Therefore, by reducing the turn-on frequencyof the second transistor T2, the frequency of writing the data signal tothe gate electrode of the fourth transistor T4 may be reduced.

For example, the frequency of the threshold compensation signal Cps iscontrolled to be less than or equal to the frequency of the first scansignal Ga1, and the frequency of the first scan signal Ga1 is controlledto be less than or equal to the frequency of the light-emitting controlsignal EM, thereby achieving the first display mode.

For example, when the pixel circuit is in the first display mode, theworking process of the pixel circuit in one display frame furtherincludes a reset phase s5, so as to implement to reset the firstelectrode of the light-emitting element 120 without refreshing the datasignal.

FIG. 4D is a circuit timing diagram of another pixel circuit provided byat least one embodiment of the disclosure, that is, the circuit timingdiagram of the pixel circuit in the first display mode.

For example, as shown in FIG. 4D, in the first display mode, eachdisplay frame included in the display screen may be the display frame“frame” shown in FIG. 4D. Taking the signal period of the light-emittingcontrol signal EM as the criterion, in the first display mode, eachdisplay frame includes at least four signal periods. For example, eachdisplay frame frame includes a first sub-frame Sub-Frame1 and at leastone second sub-frame Sub-Frame2. The first sub-frame Sub-Frame1 isconfigured to complete the refreshing of the data signal, and the secondsub-frame Sub-Frame2 is configured to maintain the display of the imagecorresponding to the data signal and reset the first electrode of thelight-emitting element 120. It should be noted that in the first displaymode, the number of the second sub-frame Sub-Frame2 in each displayframe may be set according to actual design requirements. In addition,the relative positional relationship between the first sub-frameSub-Frame1 and the second sub-frame Sub-Frame2 in each display frame mayalso be set according to actual conditions, and the present disclosuredoes not limit this.

For example, the “Data” in FIG. 4D represents the change of the gatevoltage of the fourth transistor T4, and the hexagon represents that thesignal is written to the gate electrode of the fourth transistor T4 atthis time, that is, the data signal of the data signal terminal istransmitted to the gate electrode of the fourth transistor T4 throughthe third transistor T3 and the second transistor T2.

For example, as shown in FIG. 4D, in the chronological order, the firstsub-frame Sub-Frame1 includes an initialization phase s1, a data writingphase s2, a light-emitting phase s3, a non-light-emitting phase s4, anda light-emitting phase s3. The signal level change at each phase and thestate change of the transistors and the light-emitting element 120caused by the signal level change are as described above, and will notbe described here again.

For example, as shown in FIG. 4D, in the chronological order, the secondsub-frame Sub-Frame2 includes a non-light-emitting phase s4, a resetphase s5, a light-emitting phase s3, a non-light-emitting phase s4, anda light-emitting phase s3. Here, the related descriptions of thelight-emitting phase s3 and the non-light-emitting phase s4 are asdescribed above, and will not be repeated here.

For example, the driving method further includes a reset phase s5. Inthe reset phase s5, controlling the level of the signal of thelight-emitting signal control terminal EM to be the first level,controlling the level of the signal of the first scan signal terminalGa1 to be the second level, controlling the level of the signal of thesecond scan signal terminal Ga2 to be the second level, and controllingthe level of the signal of the compensation control signal terminal Cpsto be the second level. That is to say, the light-emitting controlsignal EM is at the high level, and the first scan signal Ga1, the resetcontrol signal Rst, the second scan signal Ga2, and the compensationcontrol signal Cps are all at the low level.

Therefore, in the reset phase s5, the seventh transistor T7 is turned onunder the control of the low level of the reset control signal Rst, sothat the second initial voltage Vi2 output from the third voltageterminal Vinit2 may be supplied to the first electrode of thelight-emitting element 121 through the turned-on seventh transistor T7to reset the first electrode of the light-emitting element 121. At thesame time, the fourth transistor T4 is turned on under the control ofthe low level of the first scan signal Ga1 to provide the data voltageVda on the data signal terminal Vdata to the first electrode of thefourth transistor T4, that is, the second node N2. However, at thistime, because the second transistor T2 is turned off under the controlof the low level of the compensation control signal Cps, the datavoltage Vda cannot be transmitted to the gate electrode of the fourthtransistor T4 to achieve the refresh of the data signal, therebyreducing the refresh frequency of the data signal and achieving thefirst display mode. The first transistor T1 is turned off under thecontrol of the low level of the second scan signal Ga2, the thirdtransistor T3 is turned off under the control of the high level of thefirst scan signal Ga1, the fifth transistor T5 is turned off under thecontrol of the high level of the light-emitting control signal EM, andthe sixth transistor T6 is turned off under the control of the highlevel of the light-emitting control signal EM.

It can be seen from FIG. 4D, in the first display mode, the first scancontrol signal Ga1 still maintains a high-frequency refresh frequency,so as to reset the first electrode of the light-emitting element 120 andavoid the flicker problem in the first display mode. By reducing thefrequency of the threshold compensation signal Cps, the low-frequencyrefresh of the data signal is implemented on the premise that the firstelectrode of the light-emitting element 120 is reset at a highfrequency.

In addition, the transistors in the embodiment of the present disclosureare described by taking a case that the first transistor T1 and thesecond transistor T2 are N-type transistors and the third transistor T3to the seventh transistor T7 are P-type transistors as an example, inthis case the first electrode of the transistor is the source electrode,and the second electrode of the transistor is the drain electrode. Itshould be noted that the present disclosure includes but is not limitedto this. For example, the first transistor T1 and the second transistorT2 may be P-type transistors, and the third transistor T3 to the seventhtransistor T7 may all be N-type transistors, in this case, the firstelectrode of the transistor is the drain electrode, and the secondelectrode of the transistor is the source electrode, as long asrespective electrodes of a selected type transistor are correspondinglyconnected in accordance with respective electrodes of a correspondingtransistor in the embodiments of the present disclosure, and thecorresponding voltage terminals provide corresponding high or lowvoltages.

It should be noted that the circuit timing diagrams shown in FIG. 4A toFIG. 4D provided by the present disclosure are only schematic, and thespecific timing of the pixel circuit may be set, modified, and combinedaccording to actual application scenarios, and is not specificallylimited by the present disclosure.

FIG. 5 is a schematic diagram of a pixel circuit provided by at leastone embodiment of the present disclosure.

As shown in FIG. 5 , the pixel circuit 121′ includes a drivingsub-circuit 122, a data writing sub-circuit 123, a first light-emittingcontrol sub-circuit 124, a second light-emitting control sub-circuit125, a compensation sub-circuit 126, a first reset sub-circuit 127′, astorage sub-circuit 128, and a second reset sub-circuit 129. The pixelcircuit 121′ is configured to generate a driving current to control thelight-emitting element 120 to emit light.

For example, the first reset sub-circuit of the pixel circuit includesthe first transistor T1′, the threshold compensation sub-circuitincludes the second transistor T2, the storage sub-circuit 128 includesthe first capacitor Cst, the data writing sub-circuit 123 includes thethird transistor T3, the driving sub-circuit 122 includes the fourthtransistor T4, the first light-emitting control sub-circuit 124 includesthe fifth transistor T5, the second light-emitting control sub-circuit125 includes the sixth transistor T6, and the second reset sub-circuit129 includes the seventh transistor T7.

For example, the first transistor T1′, the third transistor T3 to theseventh transistor T7 are LTPS thin film transistors, and the secondtransistor T2 is the LTPO thin film transistor.

The gate electrode of the first transistor T1 is electrically connectedwith the first scan signal terminal Ga1, the first electrode of thefirst transistor T1 is electrically connected with the second voltageterminal Vinit1, and the second electrode of the first transistor T1 iselectrically connected with the second electrode of the fourthtransistor T4; the gate electrode of the second transistor T2 iselectrically connected with the light-emitting control signal terminalEM, the first electrode of the second transistor T2 is electricallyconnected with the gate electrode of the fourth transistor T4, and thesecond electrode of the second transistor T2 is electrically connectedwith the second electrode of the fourth transistor T4; the first end ofthe first capacitor Cst is electrically connected with the gateelectrode of the fourth transistor T4, and the second end of the firstcapacitor Cst is electrically connected with the first voltage terminalVDD; the gate electrode of the third transistor T3 is electricallyconnected with the first scan signal terminal Ga1, the first electrodeof the third transistor T3 is electrically connected with the datasignal terminal Vdata, and the second electrode of the third transistorT3 is electrically connected with the first electrode of the fourthtransistor T4; the gate electrode of the fifth transistor T5 iselectrically connected with the light-emitting control signal terminalEM, the first electrode of the fifth transistor T5 is electricallyconnected with the first voltage terminal Vinit1, and the secondelectrode of the fifth transistor T5 is electrically connected with thefirst electrode of the fourth transistor T4; the gate electrode of thesixth transistor T6 is connected to the light-emitting signal controlterminal EM, the first electrode of the sixth transistor T6 iselectrically connected to the second electrode of the fourth transistorT4, and the second electrode of the sixth transistor T6 is electricallyconnected to the first electrode of the light-emitting element 120; thegate electrode of the seventh transistor T7 is electrically connectedwith the first scan signal terminal Ga1, the first electrode of theseventh transistor T7 is electrically connected with the third voltageterminal Vinit2, and the second electrode of the seventh transistor T7is electrically connected with the second electrode of the sixthtransistor T6.

Like the pixel circuit 121, only one leakage path exists at the controlterminal of the driving sub-circuit 122 of the pixel circuit 121′, whichcan optimize the Flicker problem of the display screen. In addition,because the second transistor T2 is not located on the leakage path atthis time, the second transistor T2 may be set as an LTPS thin filmtransistor, and the LTPS thin film transistor has a small volume, whichcan reduce the layout space of the pixel circuit and improve theresolution of the display panel.

In addition, as mentioned above, the second transistor T2 is controlledby the signal from the light-emitting signal control terminal EM, whichcan increase the charging time and is more conducive to the display ofthe image in the high-frequency display mode.

In addition, the third transistor T3, the first transistor T1′, and theseventh transistor T7 in the pixel circuit 121′ are all controlled bythe signal of the first scan signal terminal Ga1, so that a group of GOAsignals may be reduced, which is beneficial to the narrow frame designof the display panel, reduces the wiring space of the pixel circuit, andfurther improves the resolution of the display panel.

For example, like the pixel circuit 121, the signal voltage of thesecond voltage terminal Vinit1 and the signal voltage of the thirdvoltage terminal Vinit2 in the pixel circuit 121′ may still be designeddifferently. For example, the voltage value of the signal of the thirdvoltage terminal Vinit2 is greater than the voltage value of the signalof the second voltage terminal Vinit1, so as to increase the stabilityof the device and further ameliorate the flicker problem of the screen.

In addition, when the signal of the light-emitting control signalterminal EM is a PWM signal, the control terminal of the secondtransistor T2 needs to be electrically connected to the compensationcontrol signal terminal Cps.

The driving method for the pixel circuit 121′ may be set by referring tothe corresponding description in combination with the circuit timingdiagrams shown in FIG. 4A to FIG. 4D, which will not be repeated here.

For the present disclosure, the following statements should be noted:

-   -   (1) The accompanying drawings of the embodiment(s) of the        present disclosure involve only the structure(s) related to the        embodiment(s) of the present disclosure, and other structure(s)        can be referred to common design(s).    -   (2) For the purpose of clarity only, in accompanying drawings        for illustrating the embodiment(s) of the present disclosure,        the thickness and size of a layer or a structure may be        enlarged. However, it should be understood that, in the case in        which a component or element such as a layer, film, region,        substrate or the like is referred to be “on” or “under” another        component or element, the component or element may be “directly”        “on” or “under” the another component or element or a component        or element is interposed therebetween.    -   (3) In case of no conflict, the embodiments of the present        disclosure and the features in the embodiment(s) can be combined        with each other to obtain new embodiment(s).

What have been described above are only specific implementations of thepresent disclosure, the protection scope of the present disclosure isnot limited thereto, and the protection scope of the present disclosureshould be based on the protection scope of the claims.

What is claimed is:
 1. A pixel circuit, comprising a drivingsub-circuit, a data writing sub-circuit, a first light-emitting controlsub-circuit, a second light-emitting control sub-circuit, a compensationsub-circuit, and a first reset sub-circuit, and configured to generate adriving current to control a light-emitting element to emit light,wherein the driving sub-circuit comprises a control terminal, a firstterminal, and a second terminal; the data writing sub-circuit iselectrically connected to the first terminal of the driving sub-circuitand a data signal terminal, and is configured to write a data signal ofthe data signal terminal into the first terminal of the drivingsub-circuit in response to a signal of a first scan signal terminal; thecompensation sub-circuit is electrically connected to the secondterminal of the driving sub-circuit and the control terminal of thedriving sub-circuit, and is configured to perform threshold compensationon the driving sub-circuit in response to a signal of a compensationcontrol signal terminal; the first reset sub-circuit is electricallyconnected to the second terminal of the driving sub-circuit and a secondvoltage terminal, and is configured to write a signal of the secondvoltage terminal into the second terminal of the driving sub-circuit inresponse to a signal of a second scan signal terminal; wherein thecompensation sub-circuit comprises a second transistor, the data writingsub-circuit comprises a third transistor, the second transistor is anoxide transistor, and an active layer type of the second transistor isdifferent from an active layer type of a transistor comprised in atleast one selected from a group consisting of the driving sub-circuit,the data writing sub-circuit, the first light-emitting controlsub-circuit, and the second light-emitting control sub-circuit; andwherein a duration when the second transistor is turned on for one timeis larger than a duration when the third transistor is turned on for onetime.
 2. The pixel circuit according to claim 1, wherein the first resetsub-circuit comprises a first transistor, and the first transistor is anoxide transistor or a low temperature polysilicon transistor.
 3. Thepixel circuit according to claim 1, further comprising a second resetsub-circuit, wherein the second reset sub-circuit is electricallyconnected to a first electrode of the light-emitting element and a thirdvoltage terminal, and is configured to write a signal of the thirdvoltage terminal into the first electrode of the light-emitting elementin response to a signal of a reset control signal terminal to reset thefirst electrode of the light-emitting element.
 4. The pixel circuitaccording to claim 3, wherein the first scan signal terminal and thereset control signal terminal are connected to an identical signal line.5. The pixel circuit according to claim 4, wherein in a case where thepixel circuit is in a first display mode, a turn-on frequency of thethird transistor is greater than a turn-on frequency of the secondtransistor, and in a case where the third transistor and the secondtransistor are both turned on, the data signal is transmitted to thecontrol terminal of the driving sub-circuit.
 6. The pixel circuitaccording to claim 3, wherein a voltage value of the signal of the thirdvoltage terminal is greater than a voltage value of the signal of thesecond voltage terminal.
 7. The pixel circuit according to claim 3,wherein the second reset sub-circuit comprises a seventh transistor, afirst electrode of the seventh transistor is electrically connected withthe third voltage terminal, and a second electrode of the seventhtransistor is electrically connected with the first electrode of thelight-emitting element.
 8. The pixel circuit according to claim 3,wherein the second reset sub-circuit comprises a seventh transistor, ina case where the pixel circuit is in a first display mode, a turn-onfrequency of the seventh transistor is greater than a turn-on frequencyof the second transistor.
 9. The pixel circuit according to claim 3,wherein the second reset sub-circuit comprises a seventh transistor, andthe duration when the second transistor is turned on for one time islarger than a duration when the seventh transistor is turned on for onetime.
 10. The pixel circuit according to claim 3, wherein the firstreset sub-circuit comprises a first transistor and the second resetsub-circuit comprises a seventh transistor, a channel width of theseventh transistor ranges from 1.5 μm to 3 μm, and a channel length ofthe seventh transistor ranges from 2 μm to 4 μm, and a channel width ofthe first transistor T1 ranges from 1.5 μm to 3 μm, and a channel lengthof the first transistor ranges from 2 μm to 4 μm.
 11. The pixel circuitaccording to claim 3, wherein the first reset sub-circuit comprises afirst transistor and the second reset sub-circuit comprises a seventhtransistor, a ratio of a channel length of the first transistor to achannel length of the seventh transistor is 1 to
 2. 12. The pixelcircuit according to claim 3, wherein a voltage range of the secondvoltage terminal ranges from −2V to −6V, and a voltage range of thethird voltage terminal ranges from −2V to −5V.
 13. The pixel circuitaccording to claim 1, further comprising a storage sub-circuit, whereinthe storage sub-circuit comprises a first capacitor, and the drivingsub-circuit comprises a fourth transistor, the control terminal of thedriving sub-circuit comprises a gate electrode of the fourth transistor,the first terminal of the driving sub-circuit comprises a firstelectrode of the fourth transistor, and the second terminal of thedriving sub-circuit comprises a second electrode of the fourthtransistor; a gate electrode of the second transistor is electricallyconnected with the compensation control signal terminal, a secondelectrode of the second transistor is electrically connected with thesecond electrode of the fourth transistor, and a first electrode of thesecond transistor is electrically connected with the gate electrode ofthe fourth transistor; a first end of the first capacitor iselectrically connected with the gate electrode of the fourth transistor,and a second end of the first capacitor is electrically connected with afirst voltage terminal; a gate electrode of the third transistor iselectrically connected with the first scan signal terminal, a firstelectrode of the third transistor is electrically connected with thedata signal terminal, and a second electrode of the third transistor iselectrically connected with the first electrode of the fourthtransistor.
 14. The pixel circuit according to claim 1, wherein thefirst light-emitting control sub-circuit comprises a fifth transistor,and the second light-emitting control sub-circuit comprises a sixthtransistor; a gate electrode of the fifth transistor is electricallyconnected with a light-emitting signal control terminal, a firstelectrode of the fifth transistor is connected with a first voltageterminal, and a second electrode of the fifth transistor is electricallyconnected with the first terminal of the driving sub-circuit; a gateelectrode of the sixth transistor is electrically connected with thelight-emitting signal control terminal, a first electrode of the sixthtransistor is electrically connected with the second terminal of thedriving sub-circuit, and a second electrode of the sixth transistor iselectrically connected with a first electrode of the light-emittingelement.
 15. The pixel circuit according to claim 14, wherein in a casewhere the pixel circuit is in a first display mode, a turn-on frequencyof the fifth transistor and a turn-on frequency of the sixth transistorboth are greater than a turn-on frequency of the second transistor. 16.The pixel circuit according to claim 1, wherein the first resetsub-circuit comprises a first transistor, a gate electrode of the firsttransistor is electrically connected with the second scan signalterminal, a first electrode of the first transistor is electricallyconnected with the second terminal of the driving sub-circuit, and asecond electrode of the first transistor is electrically connected withthe second voltage terminal.
 17. A display device, comprising aplurality of sub-pixels arranged in an array, wherein each sub-pixelcomprises a pixel circuit and a light-emitting element, the pixelcircuit comprises a driving sub-circuit, a data writing sub-circuit, afirst light-emitting control sub-circuit, a second light-emittingcontrol sub-circuit, a compensation sub-circuit, and a first resetsub-circuit, and is configured to generate a driving current to controlthe light-emitting element to emit light, the driving sub-circuitcomprises a control terminal, a first terminal, and a second terminal;the data writing sub-circuit is electrically connected to the firstterminal of the driving sub-circuit and a data signal terminal, and isconfigured to write a data signal of the data signal terminal into thefirst terminal of the driving sub-circuit in response to a signal of afirst scan signal terminal; the compensation sub-circuit is electricallyconnected to the second terminal of the driving sub-circuit and thecontrol terminal of the driving sub-circuit, and is configured toperform threshold compensation on the driving sub-circuit in response toa signal of a compensation control signal terminal; the first resetsub-circuit is electrically connected to the second terminal of thedriving sub-circuit and a second voltage terminal, and is configured towrite a signal of the second voltage terminal into the second terminalof the driving sub-circuit in response to a signal of a second scansignal terminal; wherein the compensation sub-circuit comprises a secondtransistor, the data writing sub-circuit comprises a third transistor,the second transistor is an oxide transistor, and an active layer typeof the second transistor is different from an active layer type of atransistor comprised in at least one selected from a group consisting ofthe driving sub-circuit, the data writing sub-circuit, the firstlight-emitting control sub-circuit, and the second light-emittingcontrol sub- circuit; and wherein a duration when the second transistoris turned on for one time is larger than a duration when the thirdtransistor is turned on for one time.
 18. The display device accordingto claim 17, wherein second scan signal terminals of pixel circuits ofsub-pixels located in an i-th row and compensation control signalterminals of pixel circuits of sub-pixels located in an (i−1)-th row areconnected to an identical signal line, where i is a positive integergreater than 1 and i is less than or equal to a total number of rows ofthe plurality of sub-pixels.
 19. A driving method for driving a pixelcircuit, wherein the pixel circuit comprises a driving sub-circuit, adata writing sub-circuit, a first light-emitting control sub-circuit, asecond light-emitting control sub-circuit, a compensation sub-circuit,and a first reset sub-circuit, and is configured to generate a drivingcurrent to control a light-emitting element to emit light, the drivingsub-circuit comprises a control terminal, a first terminal, and a secondterminal; the data writing sub-circuit is electrically connected to thefirst terminal of the driving sub-circuit and a data signal terminal,and is configured to write a data signal of the data signal terminalinto the first terminal of the driving sub-circuit in response to asignal of a first scan signal terminal; the compensation sub-circuit iselectrically connected to the second terminal of the driving sub-circuitand the control terminal of the driving sub-circuit, and is configuredto perform threshold compensation on the driving sub-circuit in responseto a signal of a compensation control signal terminal; the first resetsub-circuit is electrically connected to the second terminal of thedriving sub-circuit and a second voltage terminal, and is configured towrite a signal of the second voltage terminal into the second terminalof the driving sub-circuit in response to a signal of a second scansignal terminal; wherein the compensation sub-circuit comprises a secondtransistor, the data writing sub-circuit comprises a third transistor,the second transistor is an oxide transistor, and an active layer typeof the second transistor is different from an active layer type of atransistor comprised in at least one selected from a group consisting ofthe driving sub-circuit, the data writing sub-circuit, the firstlight-emitting control sub-circuit, and the second light-emittingcontrol sub-circuit, and wherein a duration when the second transistoris turned on for one time is larger than a duration when the thirdtransistor is turned on for one time; wherein a working process of thepixel circuit in one display frame comprises an initialization phase, adata writing phase, and a light-emitting phase, the driving methodcomprises: in the initialization phase, controlling a level of thesignal of the first scan signal terminal to be a first level,controlling a level of the signal of the second scan signal terminal tobe the first level, and controlling a level of the signal of thecompensation control signal terminal to be the first level; in the datawriting phase, controlling the level of the signal of the first scansignal terminal to be a second level, controlling the level of thesignal of the second scan signal terminal to be the second level, andcontrolling the level of the signal of the compensation control signalterminal to be the first level; in the light-emitting phase, controllingthe level of the signal of the first scan signal terminal to be thefirst level, controlling the level of the signal of the second scansignal terminal to be the second level, and controlling the level of thesignal of the compensation control signal terminal to be the secondlevel.
 20. The driving method according to claim 19, wherein the workingprocess of the pixel circuit in the one display frame further comprisesa non-light-emitting phase, the first light-emitting control sub-circuitis electrically connected to the first terminal of the drivingsub-circuit and a first voltage terminal, and is configured to achieve aconnection between the driving sub-circuit and the first voltageterminal to be turned on or off in response to a signal of alight-emitting signal control terminal; the second light-emittingcontrol sub-circuit is electrically connected to the second terminal ofthe driving sub-circuit and a first electrode of the light-emittingelement, and is configured to achieve a connection between the drivingsub-circuit and the light-emitting element to be turned on or off inresponse to the signal of the light-emitting signal control terminal;the driving method further comprises: in the initialization phase,controlling a level of the signal of the light-emitting signal controlterminal to be the first level; in the data writing phase, controllingthe level of the signal of the light-emitting signal control terminal tobe the first level; in the light-emitting phase, controlling the levelof the signal of the light-emitting signal control terminal to be thesecond level; in the non-light-emitting phase, controlling the level ofthe signal of the light-emitting signal control terminal to be the firstlevel, controlling the level of the signal of the first scan signalterminal to be the first level, controlling the level of the signal ofthe second scan signal terminal to be the second level, and controllingthe level of the signal of the compensation control signal terminal tobe the second level; wherein in a case where the pixel circuit is in afirst display mode, the working process of the pixel circuit in the onedisplay frame further comprises a reset phase, the driving methodfurther comprises: in the reset phase, controlling the level of thesignal of the light-emitting signal control terminal to be the firstlevel, controlling the level of the signal of the first scan signalterminal to be the second level, controlling the level of the signal ofthe second scan signal terminal to be the second level, and controllingthe level of the signal of the compensation control signal terminal tobe the second level.